Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Reduction and for Path Delay Fault Testability Angela Krsti c and Kwang-Ting (Tim) Cheng Department of ECE, University of California, Santa Barbara, CA 93106 Abstract Path delay fault model is the most suitable model for detecting distributed manufacturing defects that can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs could be very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths. Our results show that it is possible to obtain circuits with a signi cant reduction in the number of paths while not increasing area and/or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points can help reducing the number of such paths in the given design.